The new Imagination DXS GPU IP boasts a wealth of new features that will make it an integral component of the cockpit, infotainment and driver assistance systems of future vehicles. It takes the scalability, flexibility and efficiency of the latest generation of the PowerVR GPU architecture, which lifts the peak performance and lays down extra compute hardware and software to deliver up to 10x increase in compute application performance compared to the previous automotive generation, IMG BXS. 

However, the most significant innovations that IMG DXS brings to the market lie in its safety package. As driver assistance systems increase in autonomy and the responsibility shifts from driver to machine, safety – the detection and handling of faults - is a growing concern for the industry. Drivers, passengers and manufacturers need to trust that the car is able to detect faults in a suitable window and manage them before accidents occur. 

Imagination is the leading supplier of GPU IP into automotive cockpit and infotainment units, and our IP is taking a growing share of the ADAS controller market. Our previous generations featured market-leading hardware and software mechanisms – such as Tile Region Protection – to reduce the overheads involved with achieving functional safety goals but our customers still felt limited by the costs involved in achieving functional safety certification via industry-standard techniques. Dual-core lockstep required a doubling of the silicon area (and cost) of a core, while workload repetition halved performance. 

The challenge presented to the Imagination engineering team by customers was to invent a practical solution for functional safety which did not incur the same costs as industry-standard techniques. 

With IMG DXS, Imagination brings the solution to the market. 

By innovating in the field of distributed functional safety, our processors can now achieve ASIL-B certification without the power, performance and area overheads of traditional methods. 

IMG DXS strategically locates a variety of safety mechanisms, from ECC to Function Specific Replication, throughout the core to achieve >90% detection for single point failures.  Each individual mechanism focuses the function and behaviour of the core under test.  As a result, not only does Distributed Safety Mechanisms reduce the runtime and area overhead, it also helps to identify the faults to a specific module or circuit – which cannot be achieved with dual-core lockstep. 

A distributed safety approach based just on pre-existing safety mechanisms would not have been sufficient to meet the requirements of the ASIL standards. To reach the >90% single point failure metric required by ASIL-B, Imagination needed to find a way to perform fault detection on processing logic that did not depend on silicon or workload duplication. 

To this end, our engineering teams created the new, patent-protected “Safety Pairs” technique which takes advantage of the inherent parallelism of today’s processors and the fact that all threads have natural idle cycles. These threads are combined into “safety pairs” upon which test vectors are run during idle time. The output of these tests are compared to detect differences (faults), and additional safety nets are built in to ensure that functional safety standards can be achieved under all scenarios. 

Find out more about the Safety Pairs technique in our white paper “Innovation in Distributed Functional Safety”

By adding Safety Pairs into Distributed Safety Mechanisms, Imagination IP can meet ASIL-B requirements for detecting errors in processing logic with 2-3x lower overheads than traditional approaches. And it isn’t just a technique for GPUs; as the white paper shows, it is also well suited to CPUs. 

Imagination has extensive experience in developing high quality solutions that meet the requirements of safety-aware markets. Our in-house capabilities span a range of sectors and standards and emphasise quality by design, giving us the ability to help customers throughout their development lifecycle, from preliminary design to end-of-life.  We fully support our customers throughout the ASIL certification process and IMG DXS ships with a safety pack that includes the Hardware Safety Manual, Hardware Safety Case Report, FMEDA and a Safety Analysis Summary Report. We are partnering with CoreAVI on the development of safety-critical drivers for Imagination GPUs. 

With IMG DXS, Imagination demonstrates an ability to apply a visionary mindset to years of experience working in the automotive industry, resulting in silicon-proven IP carefully tailored to the needs of our customers. Unlike other GPU vendors, we are truly focused on the requirements of the automotive market and this is reflected in the abilities of our processors: from the performance of our hardware-based virtualisation to the quality of our safety coverage. To find out more about what Imagination can bring to your next automotive project, book a meeting with our sales team. 

Summary of Distributed Safety Mechanisms in IMG DXS:

• ECC/Parity detect memory faults
• Watchdogs detect hardware lockups and reset the logic locally
• Dual-core Lockstep applied to the firmware controller to guarantee the task scheduler functions correctly
• Function Specific Replication is a local logic lockstep to improve confidence
• Scheduler Interlocks prevents the GPU from responding to an erroneous workload switching demand
• Pipeline Coherency checks for data hazards and pipeline stalls triggered by faulty data or processing
• Cyclic Redundancy Checks provide bus interface protection and check the integrity of compressed tile data  
• Tile Region Protection (TRP) eliminates unnecessary duplication when dual-rendering
• Safety Pairs send locally generated test vectors to processing pipelines and compare the results during natural idle time within the process pipelines
• Diverse Watchdog Timers detect GPU lock up or performance degradation