For many years, improvements in SoC performance came from process scaling and integrating more functionality onto a single die. That model is becoming harder to sustain.  Mask costs continue to rise at advanced nodes, reticle limits constrain maximum die area, and yields fall steeply as design area grows.

Automotive compounds the pressure: a modern vehicle delivers an expanding and shifting mix of workloads across a product lifecycle that can run a decade or more.

Chiplets offer a different approach. Instead of building one large, monolithic device, functionality is partitioned into smaller silicon blocks, chiplets, that are combined within a package and connected using high-bandwidth die-to-die links such as the Universal Chiplet Interconnect Express (UCIe). The system still behaves like a single SoC, but is physically distributed across several dies.

This model is already established in the datacentre and high-performance computing. It is now moving into the car. Today, the European CHASSIS program (Chiplet-based Hardware Architectures for Software-Defined Vehicles), a three-year research initiative backed by BMW, imec, Bosch and with Imagination Technologies as a contributing partner, has announced the start of its Automotive Base Die project: a 5nm chiplet designed as the central integration hub for an open, multi-vendor automotive SoC platform. Imagination is contributing its latest functionally safe GPU IP to the program, the Imagination DXS GPU.

> Read about the Automotive Base Die

Disaggregation as a Design Strategy

The motivation for chiplets is practical. Splitting a large SoC into smaller dies improves yield and helps control cost, because defect density bites harder on a big die than on several smaller ones. It also allows different functions be manufactured on the process node that suits them – a particular advantage in automotive, where stable I/O and safety components on mature, proven nodes must coexist with fast-evolving compute on the leading edge. Compared to assembling multiple discrete SoCs on a PCB, chiplets are joined together by low-voltage die-to-die links such as UCIe that can operate at under a picojoule per bit.

Just as important is modularity. With well-defined interfaces, silicon blocks can be reused across product lines. This allows systems to scale across performance points without redesigning the entire device, supporting product families with different cost and capability targets. An OEM can scale a platform across vehicle segments and performance points without redesigning the core silicon, cutting both hardware engineering and software-porting costs across the lineup.

System-Level Considerations for GPU Integration

Behind this flexibility sits a shift in where the complexity lives. In a monolithic design, interconnect behaviour and memory access patterns are internal to the device and largely invisible to the IP using them. Disaggregate that SoC and the same behaviours become explicit, system-level constraints. Bandwidth, latency, and data locality now bear directly on performance, and nowhere more than for the GPU.

In a conventional SoC, memory traffic is carefully balanced across multiple interfaces using striping and address hashing techniques, so that the available bandwidth is actually used rather than stranded behind a controller. The GPU is built on that behaviour: it treats memory as shared, balanced, and uniformly accessible.

GPU workloads also tend to be dynamic. In graphics, work is distributed across cores at runtime, and any processing block may touch any part of memory. Access patterns follow application behaviour, not fixed scheduling rules, and they can shift from frame to frame. Put those two facts together - physically distributed memory on one side, dynamic and unpredictable access on the other - and a GPU in a chiplet system strongly favours memory that behaves as if it were unified.  In a unified memory architecture (UMA), all memory is accessible with similar latency and bandwidth even when it physically sits behind different controllers or across die-to-die links. This preserves the assumptions the GPU depends on and allows bandwidth to be balanced across the system.

If memory is instead partitioned into separate, non-uniform regions (NUMA), the problem becomes harder. Isolated memory pools are fine for independent workloads, but they break down the moment GPU cores need to cooperate. In such instances Imagination GPUs can leverage software techniques to replicate specific data sets so each chiplet can access its own local copy. This addresses the challenge, but does add a level of software overhead.

Power and thermal behaviour become more visible at this level too. With several active dies sharing one package, hotspots are less uniform which means that power delivery is harder to plan, long-term reliability is reduced and product lifecycles can be shortened.  Those effects feed directly back into how work is allocated and how performance holds up under sustained load, which means the efficiency of each processing block matters more in a chiplet design, not less.

Why Imagination GPUs Map Well to Chiplet Architectures

In a chiplet-based SoC, every IP block has to a good citizen: communicating effectively with other blocks, using bandwidth efficiently and keeping power consumption low. Because the GPU is often the largest single consumer of memory traffic, its behaviour can have an outsized effect on how the whole system scales. That said, Imagination GPUs have a range of features that make them well-suited to chiplet projects like the Automotive Base Die.

Effective Communication Between Chiplet Blocks

Integration itself needs to be straightforward, with clean interfaces between different IP blocks and an ability to scale to match different performance points without redesigning the core architecture.
Our multi-core technology provides a model here for scalable chiplet solutions. For multi-core designs, the firmware processor splits each workload into slices (e.g. strips of tiles, batches of workgroups) which are logically or spatially coherent and share data access. These are assigned to each core which then executes their share of the workload. This approach allows all cores to operate concurrently and with high efficiency. Geometry workloads, which have order dependencies, are assigned per render to the array of cores.

Coordination of all this processing is handled via the XPU bus which ensures that all work is completed before processing dependent workloads.  This model already assumes that processing elements are separated and connected through defined interfaces, so it extends naturally across chiplet boundaries. The same scheduling and communication mechanisms can operate whether cores sit on the same die or on different dies, while maintaining sufficient isolation to avoid interference.

Bandwidth-Friendly Processor Architecture

Efficiency matters a lot in a multi-die system.  Power density and thermal distribution become package-level constraints, and GPUs with strong performance per watt are easier to integrate and scale.  

Imagination’s tile-based architecture aligns well with the efficiency requirements of a chiplet system. It reduces external memory bandwidth by dividing workloads into small, manageable packages and keeping intermediate data on-chip.  Compression technologies and effective caching reduce the amount of data that needs to move through the system even further.  In a chiplet system, where memory may sit behind shared interconnects, this directly reduces pressure on bandwidth and helps maintain predictable behaviour.

Safety-Critical Processing, Ready for Automotive Systems

Automotive is a primary market for chiplet technology. Here, aligning to safety regulations is key requirement when selecting processor IP. Imagination’s latest innovations in the field of distributed safety mechanisms means that our processor IP can achieve ASIL-B certification with nowhere near the traditional performance costs that come with building a safety-critical chip.

Bringing It Together

Chiplets are changing how automotive systems are built. Functionality that once concentrated into a single monolithic device is now distributed across several dies and integrated at the package level. This enables systems to scale more flexibly,  but it pushes memory architecture and interconnect efficiency to the centre of system performance.

For a GPU, the key requirement is two-fold: maintain a unified, balanced view of memory, and keep as much traffic as possible off the shared interconnect. Architectures that already optimise external memory traffic, distribute work cleanly across independent processing elements, and reach functional safety without heavy silicon overhead are structurally better suited to that environment.

For more detail on how our architecture operates within a chiplet environment,  contact us and book in a chat.